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June 2007
HYB18T512161B2F-20/25
512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HYB18T512161B2F-20/25 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512161B2F-20/25 Revision History: 2007-06, Rev. 1.1 Page All Subjects (major changes since last revision) Typo Changes
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 05152007-ZYAH-ACMZ
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HYB18T512161B2F-20/25 512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family for graphics application and describes its main characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: * Data masks (DM) for write data * 1.8 V 0.1V VDD for [-20/-25] * 1.8 V 0.1V VDDQ for [-20/-25] * Posted CAS by programmable additive latency for better * DRAM organizations with 16 data in/outputs command and data bus efficiency * Double Data Rate architecture: * Off-Chip-Driver impedance adjustment (OCD) and On- two data transfers per clock cycle Die-Termination (ODT) for better signal quality. - four internal banks for concurrent operation * Auto-Precharge operation for read and write bursts * Programmable CAS Latency: 3, 4, 5, 6, 7 * Auto-Refresh, Self-Refresh and power saving PowerDown modes * Programmable Burst Length: 4 and 8 * Average Refresh Period 7.8 s at a TCASE lower than 85 * Differential clock inputs (CK and CK) * Bi-directional, differential data strobes (DQS and DQS) are C, 3.9 s between 85 C and 95 C transmitted / received with data. Edge aligned with read * Full Strength and reduced Strength (60%) Data-Output Drivers data and center-aligned with write data. * DLL aligns DQ and DQS transitions with clock * 2kB page size * Packages: P-TFBGA-84 * DQS can be disabled for single-ended data strobe operation * RoHS Compliant Products1) * Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
TABLE 1
Ordering Information for RoHS compliant products
Product Number HYB18T512161B2F-20/25 Org. x16 Clock (MHz) 500/400 Package P-TFBGA-84
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYB18T512161B2F-20/25 512-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 15-bit address bus is used to convey row, column and bank address information in a RAS-CAS multiplexing style. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in P-TFBGA package.
The 512-Mb DDR2 DRAM is a high-speed Double-DataRate-Two CMOS DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mb device is organized as 8 Mbit x 16 I/O x 4 banks chip. These devices achieve high speed transfer rates starting at 800 Mb/sec/pin for general applications. The device is designed to comply with all DDR2 DRAM key features: 1. posted CAS with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function.
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2
2.1
Configuration
Chip Configuration
The chip configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Ball# and Buffer Type columns are explained in Table 3 and Table 4 respectively. The ball numbering for the FBGA package is depicted in Figure 1.
TABLE 2
Chip Configuration of DDR2 SDRAM
Ball# Clock Signals J8 K8 CK CK I I SSTL SSTL Clock Signal CK, Complementary Clock Signal CK Note: CK and CK are differential system clock inputs. All address and control inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossing of CK and CK (both direction of crossing) Clock Enable Note: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active PowerDown (row Active in any bank). CKE is synchronous for power down entry and exit and for self-refresh entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used asynchronously to detect self-refresh exit condition. Self-refresh termination itself is synchronous. After VREF has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Chip Select Name Ball Type Buffer Type Function
K2
CKE
I
SSTL
Control Signals K7 L7 K3 L8 Address Signals RAS CAS WE CS I I I I SSTL SSTL SSTL SSTL
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Ball# L2 L3 L1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 Data Signals G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 Data Strobe B7 A8 F7 E8 Data Mask
Name BA0 BA1 NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS UDQS LDQS LDQS
Ball Type I I I I I I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Bank Address Bus 1:0
Address Signal 12:0, Address Signal 10/Autoprecharge
Data Signal 15:0 Note: Bi-directional data bus. DQ[15:0]
Data Strobe Upper Byte Note: UDQS corresponds to the data on DQ[15:8] Data Strobe Lower Byte Note: LDQS corresponds to the data on DQ[7:0]
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Ball# B3 F3 Power Supplies A9,C1,C3,C7,C9 A1 A7,B2,B8,D2,D8 A3,E3 Power Supplies J2 E9, G1, G3, G7, G9 J1 E1, J9, M9, R1 E7, F2, F8, H2, H8 J7 A3, E3,J3,N1,P9 Not Connected
Name UDM LDM
Ball Type I I
Buffer Type SSTL SSTL
Function Data Mask Upper/Lower Byte Note: LDM and UDM are the input mask signals and control the lower or upper bytes. I/O Driver Power Supply Power Supply I/O Driver Power Supply Power Supply I/O Reference Voltage I/O Driver Power Supply Power Supply Power Supply I/O Driver Power Supply Power Supply Power Supply Not Connected On-Die Termination Control Note: ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. An EMRS(1) control bit enables or disables the ODT functionality.
VDDQ VDD VSSQ VSS VREF VDDQ VDDL VDD VSSQ VSSDL VSS
PWR PWR PWR PWR AI PWR PWR PWR PWR PWR PWR NC I
- - - - - - - - - - - - SSTL
A2, E2, R3, R7, R8, L1 NC Other Balls K9 ODT
TABLE 3
Abbreviations for Ball Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only ball. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
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TABLE 4
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
FIGURE 1
Chip Configuration, PG-TFBGA-84 (top view)
Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8] 3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device.
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2.2
512 Mbit DDR2 Addressing
TABLE 5
512-Mbit DDR2 Addressing
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes]
1) Referred to as 'colbits' 2) Referred to as 'org' 3) PageSize = 2colbitsx org/8 [Bytes
32-Mbit x 16 BA[1:0] 4 A10 / AP A[12:0] A[9:0] 10 16 2048 (2K)
Note
1) 2) 3)
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3
Functional Description
TABLE 6
Mode Register Definition (BA[1:0] = 00B)
Field BA1 BA0 PD Bits 14 13 12 w Type1) reg. addr. Description Bank Address [1] BA1 Bank Address 0B Bank Address [0] 0B BA0 Bank Address Active Power-Down Mode Select PD Fast exit 0B 1B PD Slow exit Write Recovery2) Note: All other bit combinations are illegal. 001B 010B 011B 100B 101B 110B DLL 8 w WR 2 WR 3 WR 4 WR 5 WR 6 WR 7
WR
[11:9]
w
DLL Reset DLL No 0B 1B DLL Yes Test Mode 0B TM Normal Mode 1B TM Vendor specific test mode CAS Latency Note: All other bit combinations are illegal. 010B 011B 100B 101B 110B 111B CL reserved CL 3 CL 4 CL 5 CL 6 CL 7
TM
7
w
CL
[6:4]
w
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Field BT
Bits 3
Type1) w
Description Burst Type 0B BT Sequential BT Interleaved 1B Burst Length Note: All other bit combinations are illegal. 010B BL 4 011B BL 8
BL
[2:0]
w
1) w = write only register bits 2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR [cycles] tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
TABLE 7
Extended Mode Register Definition (BA[1:0] = 01B)
Field BA1 BA0 Qoff Bits 14 13 12 w Type1) reg. addr. Description Bank Address [1] 0B BA1 Bank Address Bank Address [0] BA0 Bank Address 1B Output Disable 0B QOff Output buffers enabled QOff Output buffers disabled 1B Complement Data Strobe (DQS Output) 0B DQS Enable 1B DQS Disable Off-Chip Driver Calibration Program 000B OCD OCD calibration mode exit, maintain setting 001B OCD Drive (1) 010B OCD Drive (0) 100B OCD Adjust mode 111B OCD OCD calibration default
DQS
10
OCD [9:7] Program
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Field AL
Bits [5:3]
Type1)
Description Additive Latency Note: All other bit combinations are illegal. 000B 001B 010B 011B 100B 101B 110B AL 0 AL 1 AL 2 AL 3 AL 4 AL 5 AL 6
RTT
6,2
Nominal Termination Resistance of ODT 00B RTT (ODT disabled) 01B RTT 75 Ohm 10B RTT 150 Ohm 11B RTT 50 Ohm Off-chip Driver Impedance Control DIC Full (Driver Size = 100%) 0B 1B DIC Reduced DLL Enable 0B DLL Enable 1B DLL Disable
DIC
1
DLL
0
1) w = write only register bits
TABLE 8
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B)
Field BA1 BA0 A SRF Bits 14 13 [12:8] 7 w w Type1) Description reg. addr., Bank Address [1] 1B BA1 Bank Address Bank Address [0] BA0 Bank Address 0B Address Bus 00000B A Address bits Address Bus, High Temperature Self Refresh Rate for TCASE > 85C 0B A7 disable 1B A7 enable 2) Address Bus 0000B A Address bits
A
[6:3]
w
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Field
Bits
Type1) w
Description Address Bus, Partial Array Self Refresh for 4 Banks3) 000B PASR0 Full Array 001B PASR1 Half Array (BA[1:0]=00, 01) 010B PASR2 Quarter Array (BA[1:0]=00) 011B PASR3 Not defined 100B PASR4 3/4 array (BA[1:0]=01, 10, 11) 101B PASR5 Half array (BA[1:0]=10, 11) 110B PASR6 Quarter array (BA[1:0]=11) 111B PASR7 Not defined
Partial Self Refresh for 4 banks PASR [2:0]
1) w = write only 2) When DRAM is operated at 85C TCase 95C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh mode can be entered. 3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
TABLE 9
EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B)
Field BA1 BA0 A Bits 14 13 [12:0] w Type
1)
Description Bank Adress[1] BA1 Bank Address 1B Bank Adress[0] 1B BA0 Bank Address Address Bus[12:0] 0B A[12:0] Address bits
1) w = write only
TABLE 10
ODT Truth Table
Input Pin DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS EMRS(1) Address Bit A10 X X X 0 X 0 X X EMRS(1) Address Bit A11
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Input Pin LDM UDM
EMRS(1) Address Bit A10 X X
EMRS(1) Address Bit A11
Note: X = don't care; 0 = bit set to low; 1 = bit set to high
TABLE 11
Burst Length and Sequence
Burst Length 4 Starting Address (A2 A1 A0) x00 x01 x10 x11 8 000 001 010 011 100 101 110 111 Notes 1. PageSize and Length is a function of I/O organization:32Mb (CA[9:0]); Page Size = 2 kByte; Page Length = 1024 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
2. Order of burst access for sequential addressing is "nibblebased" and therefore different from SDR or DDR components
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4
Truth Tables
TABLE 12
Command Truth Table
Function
CKE Previous Cycle Current Cycle H H L H H H H H H H H X X L H
CS RAS
CAS
WE BA0 BA1
A[12:11]
A10 A[9:0]
Note1)2)3)
(Extended) Mode Register Set Auto-Refresh Self-Refresh Entry Self-Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write Write with AutoPrecharge Read Read with AutoPrecharge No Operation Device Deselect Power Down Entry Power Down Exit
H H H L H H H H H H H H H H L
L L L H L L L L L L L L L H H L H L
L L L X H L L L H H H H H X X H X H
L L L X H H H H L L L L H X X H X H
L H H X H L L H L L H H H X X H X H
BA X X X BA X BA BA BA BA BA X X X X
OP Code X X X X X Column Column Column Column X X X X X X X L H L H L H X X X X X X X X X Column Column Column Column X X X X
4)5)
4) 4)6) 4)6)7)
4)5) 4) 4)5) 4)5)8) 4)5)8)
Row Address
4)5)8) 4)5)8)
4) 4) 4)9)
4)9)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 2) "X" means "H or L (but a defined logic level)". 3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register. 6) VREF must be maintained during Self Refresh operation. 7) Self Refresh Exit is asynchronous. 8) Burst reads or writes at BL = 4 cannot be terminated. 9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements
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TABLE 13
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE Previous Cycle6) (N-1) Power-Down Self Refresh Bank(s)Active All Banks Idle L L L L H H H Any State other H than listed above
1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11)
Current Cycle6) (N) L H L H L L L H
Command Action (N)2) (N)2)3)RAS, CAS, WE, CS X DESELECT or NOP X DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTOREFRESH Maintain Power-Down Power-Down Exit Maintain Self Refresh Self Refresh Exit Active Power-Down Entry Precharge Power-Down Entry Self Refresh Entry
Note4)5)
7)8)11) 7)9)10)11) 8)11)12) 9)12)13)14) 7)9)10)11)15) 9)10)11)15)
7)11)14)16) 17)
Refer to the Command Truth Table
12) 13) 14) 15) 16) 17)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. CKE must be maintained HIGH while the device is in OCD calibration mode. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1)). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2xtCKE + tIH. VREF must be maintained during Self Refresh operation. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table.
TABLE 14
Data Mask (DM) Truth Table
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
DM L H
DQs Valid X
Note
1) 1)
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5
Electrical Characteristics
TABLE 15
DRAM Component Operating Temperature Range
Symbol TCASE
Parameter Operating Temperature
Rating 0 to 95
Unit C
Notes
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4) When operating this product in the 85C to 95C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". Note, when the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
5.1
Absolute Maximum Ratings
TABLE 16
Absolute Maximum Ratings
Symbol
Parameter
Rating min max 2.3 2.3 2.3 2.3 125 -55 150
Unit
Notes
VDD VDDQ VDDL VIN, VOUT TJ TSTG
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Junction Temperature Storage Temperature
-1.0 -0.5 -0.5 -0.5
V V V V C C
1) 1) 1) 1) 1) 1)2)
1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
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5.2
DC Characteristics
TABLE 17
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating Min. Typ. 1.8 1.8 1.8 0.5 x VDDQ Max. 1.9 1.9 1.9 0.51 x VDDQ
Unit
Notes
VDD VDDDL VDDQ VREF VTT
Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage
1.7 1.7 1.7 0.49 x VDDQ
V V V V V
1)2) 1)2) 1)2) 3)4) 5)
VREF - 0.04
VREF
VREF + 0.04
1) HYB18T512161B2F-20/25 2) VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 3) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4) Peak to peak ac noise on VREF may not exceed 2% VREF (dc) 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF.
TABLE 18
ODT DC Electrical Characteristics
Parameter / Condition Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm Deviation of VM with respect to VDDQ / 2
1)
Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM
Min. 60 120 40 -6.00
Nom. 75 150 50 --
Max. 90 180 60 + 6.00
Unit %
Note
1)
1)
1)
2)
Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) - VIL(ac)) /(I(VIHac) - I(VILac)). 2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) - 1) x 100%
TABLE 19
Input and Output Leakage Currents
Symbol IIL IOL Parameter / Condition Input Leakage Current; any input 0 V < VIN < VDD Output Leakage Current; 0 V < VOUT < VDDQ Min. -2 -5 Max. +2 +5 Unit A A Notes
1) 2)
1) all other pins not under test = 0 V 2) DQ's, LDQS, LDQS, UDQS, UDQS, DQS, DQS are disabled and ODT is turned off
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5.3
DC & AC Characteristics
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS signals are internally disabled and don't care.
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
TABLE 20
DC & AC Logic Input Levels
Symbol Parameter DC input logic high DC input low AC input logic high AC input low Min. Max. Units V V V V
VIH(dc) VIL(dc) VIH(ac) VIL(ac)
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
VREF + 0.250
--
VREF - 0.250
TABLE 21
Single-ended AC Input Test Conditions
Symbol Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum Slew Rate Value 0.5 x VDDQ 1.0 1.0 Unit V V V / ns Notes
1) 1) 2)3)
VREF VSWING.MAX
SLEW
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to VIL(ac).MAX for falling edges as shown in Figure 2 3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.
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FIGURE 2
Single-ended AC Input Test Conditions Diagram
TABLE 22
Differential DC and AC Input and Output Logic Levels
Symbol Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross point input voltage AC differential cross point output voltage Min. -0.3 0.25 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 Max. Unit -- -- V V V Notes
1) 2) 3) 4) 5)
VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac)
1) 2) 3) 4)
VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125
indicates the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR- VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc). VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac). The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
FIGURE 3
Differential DC and AC Input and Output Logic Levels Diagram
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5.4
Output Buffer Characteristics
TABLE 23
Full Strength Calibrated Pull-up Driver Characteristics
Voltage (V)
Calibrated Pull-up Driver Current [mA] Nominal(18 Nominal Minimum1) Nominal Low2)(18.75 Ohms) ohms)3) (21 Ohms) Nominal High2)(17.25 Ohms) -11.8 -17.4 -23.0 Nominal Maximum4) (15 Ohms) -13.3 -20.0 -27.0
0.2 0.3 0.4
1) 2) 3) 4)
-9.5 -14.3 -18.3
-10.7 -16.0 -21.0
-11.4 -16.5 -21.2
The driver characteristics evaluation conditions are Nominal Minimum 95 C (TCASE). VDDQ = 1.7 V, any process The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 C (TCASE), VDDQ = 1.8 V, any process The driver characteristics evaluation conditions are Nominal 25 C (TCASE), VDDQ = 1.8 V, typical process The driver characteristics evaluation conditions are Nominal Maximum 0 C (TCASE), VDDQ = 1.9 V, any process
TABLE 24
Full Strength Calibrated Pull-down Driver Characteristics
Voltage (V) Calibrated Pull-down Driver Current [mA] Nominal Minimum1) (21 Ohms) 0.2 0.3 0.4
1) 2) 3) 4)
Nominal Low2)(18.75 Ohms) 10.7 16.0 21.0
Nominal3)(18 ohms) 11.5 16.6 21.6
Nominal High2)(17.25 Ohms) 11.8 17.4 23.0
Nominal Maximum4) (15 Ohms) 13.3 20.0 27.0
9.5 14.3 18.7
The driver characteristics evaluation conditions are Nominal Minimum 95 C (TCASE). VDDQ = 1.7 V, any process The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 C (TCASE), VDDQ = 1.8V, any process The driver characteristics evaluation conditions are Nominal 25 C (TCASE), VDDQ = 1.8 V, typical process The driver characteristics evaluation conditions are Nominal Maximum 0 C (TCASE), VDDQ = 1.9 V, any process
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5.5
Input / Output Capacitance
TABLE 25
Input / Output Capacitance
Symbol CCK CDCK CI CDI CIO CDIO
Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS
Min. 1.0 -- 1.0 -- 2.5 --
Max. 2.0 0.25 1.75 0.25 3.5 0.5
Unit pF pF pF pF pF pF
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5.6
Overshoot and Undershoot Specification
TABLE 26
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS
-20 0.5 0.5 0.80 0.80
-25 0.5 0.5 0.80 0.80
Unit V V V.ns V.ns
FIGURE 4
AC Overshoot / Undershoot Diagram for Address and Control Pins
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TABLE 27
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ -20 0.9 0.9 0.23 0.23 -25 0.9 0.9 0.23 0.23 Unit V V V.ns V.ns
FIGURE 5
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
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5.7
AC Characteristics
5.7.1
Speed Grade Definitions
TABLE 28
Speed Grade Definition
Speed Grade Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 @ CL = 7 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol
-20 Min. 5 3.75 3 2.5 2.0 45 60 15 15 Max. 8 8 8 8 8 70k -- -- --
-25 Min. 5 3.75 3 2.5 -- 45 60 15 15 Max. 8 8 8 8 -- 70k -- -- --
Unit
Note
tCK tCK tCK tCK tCK tRAS tRC tRCD tRP
ns ns ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the "Reference Load for Timing Measurements" according to Chapter 7.1 only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS is defined in Chapter 7.3. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. See Chapter 7.1 for the reference load for timing measurements. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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5.7.2
AC Timing Parameters
TABLE 29
Timing Parameter by Speed Grade
List of Timing Parameters
Parameter
Symbol
-20 Min. Max. +450 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 280 WL + 0.25
-25 Min. -500 2 0.45 3 0.45 WR + tRP Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +500 -- 280 WL + 0.25 -- -- -- --
Unit Notes1)
2)3)4)5)6)
DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH tDH1 tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS
-450 2 0.45 3 0.45 WR + tRP
ps
tCK tCK tCK tCK tCK
ns ps ps
7)18)
tIS + tCK + tIH
145 -105 0.35 -450 0.35 -- WL - 0.25 20 -105 0.2 0.2 -- 525 0.6 400 2x
tIS + tCK + tIH
250 0 0.35 -500 0.35 -- WL - 0.25 125 0
8)
9)
9)
tCK
ps
9)
tCK
ps
10)
tCK
ps ps
9)
DQ and DM input setup time (single ended data tDS1 strobe) DQS falling edge hold time from CK (write cycle) tDSH DQS falling edge to CK setup time (write cycle) tDSS Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time
9)
-- --
0.2 0.2 -- 575 0.6 450
tCK tCK
11)
tHP tHZ tIH tIPW tIS tLZ(DQ) tLZ(DQS) tMRD
MIN. (tCL, tCH) --
MIN. (tCL, tCH) --
tAC.MAX
--
tAC.MAX
-- -- --
ps ps
12)
tCK
ps ps ps
12)
tAC.MIN tAC.MIN
2
tAC.MAX tAC.MAX
--
2x
tAC.MIN tAC.MIN
2
tAC.MAX tAC.MAX
--
12)
tCK
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Parameter
Symbol
-20 Min. Max. 12 -- 380 7.8 3.9 -- 1.1 0.60 -- -- -- 0.60 --
-25 Min. 0 Max. 12 -- 380 7.8 3.9 -- 1.1 0.60 -- -- -- 0.60 --
Unit Notes1)
2)3)4)5)6)
OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval
tOIT tQH tQHS tREFI
0
ns ps s s ns
13)14) 13)15) 16)
tHP-tQHS
-- -- -- 105 0.9 0.40 10 7.5 0.35 x tCK 0.40 14
tHP-tQHS
-- -- -- 105 0.9 0.40 10 7.5 0.35 x tCK 0.40 15
Auto-Refresh to Active/Auto-Refresh command tRFC period
tRPRE Read postamble tRPST Active bank A to Active bank B command period tRRD Internal Read to Precharge command delay tRTP tWPRE Write preamble Write postamble tWPST Write recovery time for write without AutotWR
Read preamble Precharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command WR
tCK tCK
ns ns
12) 12) 14)17)
tCK tCK
ns
17)
tWR/tCK
7.5 2 10 - AL 2 -- -- -- -- -- --
tWR/tCK
7.5 2 8 - AL 2 -- -- -- -- -- --
tCK
ns
18)
tWTR tXARD tXARDS tXP tXSNR tXSRD
19) 20)
tCK tCK tCK
ns
20)
tRFC +10
200
tRFC +10
200
tCK
1) VDDQ, VDD refer to Chapter 1. 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this data sheet. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS, input reference level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in Chapter 5.3 of this data sheet. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required. 9) timing is referenced to Industrial standard definition 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
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12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 14) 0 C TCASE 85 C 15) 85 C < TCASE 95 C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 18) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
5.7.3
ODT AC Electrical Characteristics
TABLE 30
ODT AC Electrical Characteristics and Operating Conditions for all bins
Symbol
Parameter / Condition
Values Min. Max. 2
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns
2.5
tCK
ns ns
2)
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
tCK tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
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6
Specifications and Conditions
TABLE 31
IDD Measurement Conditions
Parameter Operating Current - One bank Active - Precharge tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching.
Symbol
Note
1)2)3)4)5)6)
IDD0
IDD1
1)2)3)4)5)6)
Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs are floating. Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching, Data bus inputs are switching. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data bus inputs are floating. Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating. MRS A12 bit is set to "0" (Fast Power-down Exit). Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
1)2)3)4)5)6)
1)2)3)4)5)6)
IDD2Q
1)2)3)4)5)6)
IDD3P(0)
1)2)3)4)5)6)
IDD3P(1)
1)2)3)4)5)6)
Active Standby Current IDD3N All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA. Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Burst Refresh Current IDD5B tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching. Distributed Refresh Current tCK = tCK(IDD), Refresh command every tREFI = 7.8 s interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
IDD5D
1)2)3)4)5)6)
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Parameter
Symbol
Note
1)2)3)4)5)6)
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current IDD7 1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data bus is switching. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled.
4) 5) 6) 7) Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS. Definitions for IDD: see Table 32 Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7.. A = Activate, RA = Read with Auto-Precharge, D=DESELECT
1)2)3)4)5)6)7)
TABLE 32
Definition for IDD
Parameter LOW HIGH STABLE FLOATING SWITCHING Description defined as VIN VIL(ac).MAX defined as VIN VIH(ac).MIN defined as inputs are stable at a HIGH or LOW level defined as inputs are VREF = VDDQ / 2 defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes
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TABLE 33
IDD Specification
Speed Grade Symbol -20 typ. 84 93 4 42 38 26 7 47 203 192 121 5 4 206 -25 typ. 80 90 4 37 34 22 7 41 173 162 117 5 4 203 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
3) 3) 1) 2)
Unit
Note
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) MRS(12)=0 2) MRS(12)=1 3) 0 TCASE 85C
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7
7.1
Package
Package Dimension
FIGURE 6
Package Outline P-TFBGA-84 (top view)
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7.2
Package Thermal Characteristics
TABLE 34
Package thermal characteristics
JESD51 Industrial standard Board Air Flow Rth[K/W] 1s0p 0 m/s 69 1 m/s 53 3 m/s 47
Theta_jA
1)
Theta_jC2)
2s0p 0 m/s 41 1 m/s 35 3 m/s 33 5
1) Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the Industrial standard JESD-51 standard. 2) Junction to Case thermal resistance. The value has been obtained by simulation.
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Contents
1 1.1 1.2 2 2.1 2.2 3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.7.3 6 7 7.1 7.2 Overview 3 Features 3 Description 4 Configuration 5 Chip Configuration 5 512 Mbit DDR2 Addressing 9 Functional Description 10 Truth Tables 15 Electrical Characteristics 17 Absolute Maximum Ratings 17 DC Characteristics 18 DC & AC Characteristics 19 Output Buffer Characteristics 21 Input / Output Capacitance 22 Overshoot and Undershoot Specification 23 AC Characteristics 25 Speed Grade Definitions 25 AC Timing Parameters 26 ODT AC Electrical Characteristics 28 Specifications and Conditions 29 Package 32 Package Dimension 32 Package Thermal Characteristics 33 Contents 34 List of Tables 35 List of Figures 36
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HYB18T512161B2F-20/25 512-Mbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 512-Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Extended Mode Register Definition (BA[1:0] = 01B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Full Strength Calibrated Pull-up Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 24 Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timing Parameter by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ODT AC Electrical Characteristics and Operating Conditions for all bins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ
35
Internet Data Sheet
HYB18T512161B2F-20/25 512-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Chip Configuration, PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outline P-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ
36
Internet Data Sheet
Edition 2007-06 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com

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